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NXP Semiconductors /LPC408x_7x /PWM0 /MR2

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Interpret as MR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MATCH

Description

Match Register. Match registers are continuously compared to the PWM counter in order to control PWM output edges.

Fields

MATCH

Timer counter match value.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data